BL808
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| BL808 | |
|---|---|
 BL808C on PINE64 Ox64 | |
| CPU | T-Head C906 480MHz 64-bit (D0), T-Head E907 320MHz 32-bit (M0), T-Head E902 150MHz 32-bit (LP) |
| Memory | 160K WRAM, 64K OCRAM, 32/64MiB pSRAM |
| Storage | External SPI Flash (QSPI) or integrated pne |
| Wireless | WiFi4, Bluetooth 5.x Dual Mode (BT+BLE), Zigbee / IEEE 802.15.4 |
| Package | QFN88 |
| GPIO Pins | 36/40 |
| Release date | 2022 |
The BL808 System on a Chip SoC from Bouffalo Labs is a versatile platform for embedded systems and Internet of Things (IoT) applications. It is composed of three different RISC-V cores, one 64-bit and two 32-bit. Each core is optimized for different tasks. The main C906 core of the BL808 SoC is capable of running the Linux operating system thanks to its MMU.
Overview
The BL808 Features three heterogenous riscv cores
- T-Head C906 480MHz 64-bit RISC-V CPU [1]
- T-Head E907 320MHz 32-bit RISC-V CPU [2]
- T-Head E902 150MHz 32-bit RISC-V CPU [3]
Applications
There are some development boards that are using the BL808 including the Pine64 Ox64 and the Sipeed M1s Dock.
Technical Specifications
SoC Features
Taken directly from the datasheet:
Wireless
- Wi-Fi 802.11 b/g/n
- Bluetooth® 5.x Dual-mode (BT+BLE)
- Zigbee / IEEE 802.15.4
MCU
- RTC timer up to one year
- General purpose timers
- DMA channels
- JTAG development support
- XIP QSPI flash support
Audio
- ADC*2 (Mic*2 or Mic*1+Line-in)
- DAC*1 (Speaker)
- Sample Rate 8~192KHz, 24bit
Video/Image/Display
- MJPEG , H264 (Baseline/Main)
- Maximum resolution:2M(1920x1080)
- Video encoding format:
- MJPEG and H264 (Baseline/Main)
- 1920x1080 @ 30fps + 640x480 @ 30fps
- Up to 8-ROI(region-of-interest)
- Camera Sensor interface: DVP and MIPI-CSI
- Display interface: SPI, DBI, DPI(RGB), MIPI-DSI
Memory
- Embedded 32/64MB DRAM
- Support max 128MB SPI-Nor Flash
- Support max 256MB SPI-NAND Flash
Security
- Secure boot; Secure debug
- XIP QSPI On-The-Fly AES Decryption (OTFAD)
- Support sensitive SW isolation (TrustZone)
- AES-CBC/CCM/GCM/XTS modes
- MD5, SHA-1/224/256/384/512
- TRNG (True Random Number Generator)
- PKA (Public Key Accelerator) for RSA/ECC
Peripherals
- USB 2.0 HS OTG
- Ethernet RMII Interface
- SD-card interface
- 4 UART interfaces
- 2 SPI interfaces
- 4 I2C interfaces
- 8 PWM channels
- I2S interface
- PDM interface
- General-Purpose ADC
- General-Purpose DAC
- General analog comparators (ACOMP)
- PIR (Passive Infra-Red) detection
- IR remote HW accelerator
- Support 12-Channel Touch
- Flexible 36 or 40 GPIOs
Clock
- Support XTAL 24/26/32/38.4/40 MHz
- Support XTAL 32/32.768 KHz
- Internal RC 32KHz/32MHz oscillator
- Internal System PLLs
Cores
D0: T-Head C906
- Instruction set is XuanTie ISA
- Compatible with RV64IMA[F][D]C[V]
- Microarchitecture is single-issue in-order execution
- 5-stage integer pipeline
- General purpose register: 32 64-bit GPR, 32 64-bit FGPR, 32 128-bit VGPR
- Vector execution unit supports SIMD calculations for INT8/INT16/INT32/INT64 and FP16/FP32/FP64 and BFP16 new data format
- Optional I-Cache and D-Cache, 8-64KB
- Mixed branch prediction with an optional 8Kb/16Kb branch history table, branch target buffer, and return address stack
- Bus interface is a 128-bit single bus access interface
- MMU supports Sv39 memory management with 128/256/512 TLB table entry
- Optional 0-16 protection regions for physical memory protection
- PLIC interrupt controller supports up to 1023 external interrupts
- RISC-V standard performance monitoring unit
- Support for RISC-V Debug protocol standard and third-party IDE/debugging software such as IAR, Segger, Lauterbach.
M0: T-Head E907
- Instruction set is XuanTie ISA
- Compatible with RV32IMA[F][D]C[P]
- Microarchitecture is single-issue in-order execution
- Integer has a 5-stage pipeline, and floating-point has a 7-stage pipeline
- General purpose register: 32 32-bit GPR, 32 32-bit/64-bit FGPR
- Optional I-Cache and D-Cache with a size range of 2K-32KB
- Mixed branch prediction with branch history table, branch target buffer, and return address stack with configurable sizes
- Double bus interfaces with 1 master interface and 1 low-latency peripheral interface
- Optional 0-16 protection regions for memory protection
- Supports unaligned memory read/write
- CLIC interrupt controller supports up to 240 interrupts
- RISC-V standard performance monitoring unit
- Support for RISC-V Debug protocol standard and third-party IDE/debugging software such as IAR, Segger, Lauterbach.
LP: T-Head E902
- Instruction set is XuanTie ISA
- Compatible with RV32E[M]C
- Pipeline is 2-stage
- Privilege modes: M U modes
- General purpose register: 16 32-bit GPR
- Double bus with separate instruction and data buses
- Optional 0-16 protection regions for memory protection
- Tightly coupled IP includes interrupt controller and timer
- Optional slow or fast multiplier
- ~10K gates for the minimum configuration
Documentation
Official SoC information