Bouffalo ISP Protocol V1: Difference between revisions

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Every chip using ISP Protocol V1 have ability to get into ISP mode by specifying voltage level on specific pin during boot time. This mechanism is implemented within BootROM code.
Every chip using ISP Protocol V1 have ability to get into ISP mode by specifying voltage level on specific pin during boot time. This mechanism is implemented within BootROM code.


{{Collapse top|title=Example hardware layout}}
{{Collapse top|title=Example hardware layout|width=unset}}
Example is taken from BL602 Datasheet
Example is taken from BL602 Datasheet



Revision as of 20:03, 19 May 2023

This page describes Bouffalo ISP Protocol V1, which is ISP protocol used to run images, write images to Flash or program fuses via UART, USB, SDIO or JTAG.

It is integrated in BL602, BL702, BL808 and BL616 series of chips, although, every series have some improvements to this protocol.

List of available interfaces for specific chips:

Chip UART USB SDIO JTAG SD Card
BL602 Series Yes No Yes ? No
BL702 Series Yes Yes No ? No
BL808C Yes Broken ? ? Broken?
BL808D Yes N/A ? ? N/A
BL606P Yes ? ? ? N/A
BL616 Series Yes Yes ? ? ?

Getting into ISP/BootROM mode

Currently, there are two ways of getting into ISP mode, which we will describe in next sections:

Via GPIO

Every chip using ISP Protocol V1 have ability to get into ISP mode by specifying voltage level on specific pin during boot time. This mechanism is implemented within BootROM code.

Example hardware layout

Example is taken from BL602 Datasheet

Bl602 bootpin layout.png

Chip Pin ISP Mode when pin is Note
BL602 Series IO8 High
BL702 Series IO28 High
BL808 Series IO39 High Multiplexed with QSPI D3 pin
BL616 Series IO2 High

Handshake